1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device that is used in the power electronics field, such as various kinds of switching power supplies.
2. Related Art
A semiconductor device such as a MOS field effect transistor (hereinafter referred to as “MOSFET”) or an insulating-gate bipolar transistor (hereinafter referred to as “IGBT”) has high-speed switching properties and a reverse-direction blocking voltage of several dozen to several hundred voltage (hereinafter referred as to the “withstand voltage”). Therefore, such semiconductor devices are widely used in a technical field regarding control systems, such as power converters for household appliances, communication devices and vehicle motors. In order to achieve downsizing, high efficiency and low power consumption of power systems using such semiconductor devices, it is necessary to lower the resistance (hereinafter referred to as the “ON resistance”) in the ON state of the semiconductor devices included in the power system. A MOSFET and an IGBT are strongly required to increase a withstand voltage and lower the ON resistance.
When a high voltage is applied to the semiconductor device in an OFF state, the drift region is normally depleted, and the high voltage is held. Since the semiconductor device such as the MOSFET or IGBT has a drift region of relatively low doping concentration to obtain a high withstand voltage, the resistance becomes higher and a ratio of the drift resistance to the ON resistance of a chip increases. As a result, the ON resistance also becomes higher. Therefore, in such semiconductor devices, there is a “trade-off” relationship between the withstand voltage and the ON resistance, and there is a limitation depending on the materials.
As the structures to reduce the drift resistance, a super junction structure has been known (see “Theory of semiconductor super junction devices” (T. Fujihira, Jpn. J. Appl. Phys., Vol. 36 (1997), p.p. 6254-6262). In the super junction structure, p-type semiconductor layers and n-type semiconductor layers are alternately disposed in a direction perpendicular to the current path in the drift region.
In an ordinary semiconductor device, when a high voltage is applied to the drain electrode, the depletion layer spreads from a pn junction plane between a p-type base region connected to a source electrode and an n-type drift region. As a result, when the intensity of the electric field at the pn junction plane reaches a critical electric field, an avalanche breakdown occurs. Therefore, the withstand voltage of the ordinary semiconductor device is determined by the doping concentration of the n-type drift region and the depletion layer length.
On the other hand, in the super junction structure, the depletion layer spreads not only from the pn junction plane between the p-type base region and the n-type drift region but also from the pn junctions between the p-type semiconductor layers and the n-type semiconductor layers in the drift region. Therefore, the electric field concentration on the pn junction plane between the p-type base region and the n-type drift region is relaxed, and the electric field in the entire drift region becomes higher. As a result, even if the doping concentration of the n-type semiconductor layers becomes higher than the doping concentration in the drift region of the ordinary semiconductor device, a high withstand voltage is achieved. Furthermore, when the semiconductor device is in the ON state, a current flows in the high-concentration n-type semiconductor layers. Therefore, the ON resistance of the super junction structure can be set to approximately ⅕ of the ON resistance in the ordinary semiconductor device having substantially the same withstand voltage as that of the super junction structure.
However, there is still a demand for further reducing the ON resistance in the super junction structure. In order to further reduce the ON resistance in the super junction structure, it is necessary to increase the doping concentration in the n-type semiconductor layers. In such a case, the n-type semiconductor layers need to be depleted so as to maintain the withstand voltage. Therefore, it is necessary to reduce the widths of the n-type semiconductor layers and the p-type semiconductor layers. That is, it is necessary to increase the aspect ratio of each of the semiconductor layers.
As the methods for forming the super junction structure, the following methods have been known. For example, there is a method in which trenches are formed by reactive ion etching (hereinafter referred to as “RIE”) on the surface of an n-type epitaxial layer, and then p-type layers are epitaxially grown (see JP-A No. 2007-12801 (Kokai)). Furthermore, there is a method for selectively forming n-type and p-type buried layers on a high-resistance epitaxial layer through ion implantation and diffusion, for stacking high-resistance epitaxial layers, and for forming n-type and p-type buried layers by ion implantation and diffusion in the same manner as the formation of the lower layers, the method being repeated multiple times (see JP-A No. 2004-14554 (Kokai)).
It is very difficult to implement the method disclosed in JP-A No. 2007-12801 (Kokai) in that a high-quality silicon is epitaxially grown inside the trenches at a high aspect ratio, and impurities have to be implanted at high controllability.
According to the method disclosed in JP-A No. 2004-14554 (Kokai), higher controllability is achieved, though the number of manufacturing steps such as ion implantations and epitaxial growths is increased. Therefore, the method is well used as the process for forming the super junction structure and has been commercialized.
However, according to the method disclosed in JP-A No. 2004-14554 (Kokai), it is necessary to adjust the thickness of each high-resistance epitaxial layer to such a thickness that the n-type and p-type diffusion layers located above and below can be connected at high concentration. Therefore, in order to achieve a high aspect ratio, it is necessary to reduce the distance between adjacent p-type and n-type diffusion layers. In doing so, however, the overlapped and cancelled-out doping concentration increases, thereby reducing a process margin.
In order to reduce the cancelled-out doping concentration, it is conceivable to reduce the diffusion length. In this case, however, the thickness of each epitaxial layer needs to be reduced so that upper and lower diffusion layers are not contacted at high concentration.
However, the total thickness of the drift region is substantially uniform. Therefore, if each of the epitaxial layers is made thinner by reducing the diffusion length, the number of manufacturing steps required for the ion implantations and the epitaxial growths increases, thereby rising the production costs.
Meanwhile, the super junction structure has a different drift region from the drift region of an ordinary double-diffusion MOS (hereinafter referred to as “DMOS”) structure. Therefore, the trade-off relationship between the withstand voltage and the ON resistance is improved. The profile of the super junction structure is a unique profile of the drift region, and depends on the p-type and n-type pillar profiles. Therefore, the profile has the electric field distribution greatly different from the electric field distribution of the DMOS. As a result, the super junction structure that the DMOS does not have has to be suitably designed in order to obtain the static properties ordinarily achieved by a switching device such as a DMOS, and also to improve an avalanche capability and reliability.
There is another known method, in which the widths or doping concentration of n-type semiconductor layers and p-type semiconductor layers of pn structures disposed in parallel is controlled to make the doping concentration higher in a p-type region on the surface-side than the doping concentration in the adjacent n-type region, and to make the doping concentration lower in the p-type region on the bottom-side than the doping concentration in the n-type region, thereby improving the electric field distributions at the pn structure portions and the avalanche capability (see JP-A No. 2004-72068 (Kokai)). The method disclosed in JP-A No. 2004-72068 (Kokai) has to design the profile of the pn structures in the drift region in order to maintain the switching properties and the device reliability, in addition to improvement of the avalanche capability. For example, the method disclosed in JP-A No. 2004-72068 (Kokai) designs the profile for securing the device reliablity by providing a peak point of the electric field in the middle of the drift region and by setting the avalanche point away from the gate electrode.
However, if the peak point of the electric field is provided in the middle of the drift region by the method disclosed in JP-A No. 2004-72068 (Kokai), the gate potential varies via the gate oxide film due to the avalanche breakdown caused in the vicinity of the gate electrode, and a feedback current flows through the gate electrode. As a result, the avalanche capability might be adversely affected (see S.-C. Lee, K.-H. Oh, Jang, J.-G. Lee, S.-S. Kim, and C.-M. Yun, “Investigation of Gate Oscillation of Power MOSFETs Induced by Avalanche Mode Operation”, Power Semiconductor Devices and IC's, 2007 IEEE International Symposium on 27-30 May, 2006, p.p. 113-116).
In the other document of “Investigation of Gate Oscillation of Power MOSFETs Induced by Avalanche Mode Operation”, the influence on the avalanche capability is described. However, according to the method disclosed in JP-A No. 2004-72068 (Kokai), the switching properties are also affected, because there is a high-electric-field portion in the vicinity of the gate electrode. As a result, the feedback current flows through the gate electrode, thereby causing switching noise.
According to the method disclosed in JP-A No. 2004-72068 (Kokai), when the feedback current flowing through the gate electrode increases, the reliability of the gate insulating film becomes lower. For example, when carriers generated by the avalanche breakdown are trapped in the gate insulating film, the threshold voltage of devices varies, and the properties (the threshold voltage and the drain-source leakage) also vary.
Furthermore, according to the method disclosed in JP-A No. 2004-72068 (Kokai), the spread of the depletion layer depending on the drain-source voltage varies due to the profiles of the pn structures. As a result, the change in capacity at the time of switching operation also varies.
As above, according to conventional super junction structures, it is difficult to improve the avalanche capability and the device reliability at the same time.